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- Abe
Frequent Contributor
There are a couple of issues.. check out this code and try if it works.. this is the correct way to implement a LFSR.
`timescale 1ns/1ns module Memorygame ( input wire clk, input wire rst_n, output reg [3:0] out ); integer count; reg clk_1hz; wire lf; // linear feedback of XORed bits. always @ (posedge clk or negedge rst_n) begin // slows our clock from 50mhz to 1hz if(!rst_n) begin count = 0; clk_1hz <= 1'b0; end else begin if (count<250000) count <= count + 1; else begin clk_1hz <= ~clk_1hz; count <= 0; end end end //always assign lf = !(out[3] ^ out[0]); always @(posedge clk_1hz or negedge rst_n) begin if(!rst_n) out <= 4'b0000; else begin out <= {out[2],out[1], out[0], lf}; end end //always