My 2nd Intel FPGA design

Hi,

By referring to Max 10 GPIO user guide, Figure 1, 10M02 and 10M04 devices are migratable. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf

However, there is no information available to confirm if it is exact drop in replacement part. You would need to further verify thru Quartus Prime software with migration feature enable. When the migration feature is enabled in your design, you should always follow the common pin placement as stated in the Quartus Prime software Pin Migration Window in the Pin Planner.

Thank you

Regards,

Chia Ling

Hi Chia,

I understand that the 10M02 and 10M04 aren't pin-to-pin compatible. But I'm concerned that maybe the PCB changes needed to migrate to the 10M04 aren't just rerouting the traces & repositioning some components based on the new pin positions of the 10M04. I do believe it's just that. It's just that this is my 2nd design using those FPGAs and I am indeed worried about making a beginner's mistake.

And also, a concern that I have is that the Pin Connection Guidelines for the MAX10 family says that unused CLK and PLL pins should be tied to VCCIO or GND. However, on my previous board, I left them open, and (maybe out of luck) everything worked fine. But do I indeed need to tie those to VCCIO or GND?

Hi,

I would like to understand if you manage to get the common pin placement when you enabled the migration feature in your design. You could further confirm the common pin location as stated in the Quartus Prime software pin migration window.

Thank you

Regards,

Chia Ling