My 2nd Intel FPGA design

Hi Chia,

I understand that the 10M02 and 10M04 aren't pin-to-pin compatible. But I'm concerned that maybe the PCB changes needed to migrate to the 10M04 aren't just rerouting the traces & repositioning some components based on the new pin positions of the 10M04. I do believe it's just that. It's just that this is my 2nd design using those FPGAs and I am indeed worried about making a beginner's mistake.

And also, a concern that I have is that the Pin Connection Guidelines for the MAX10 family says that unused CLK and PLL pins should be tied to VCCIO or GND. However, on my previous board, I left them open, and (maybe out of luck) everything worked fine. But do I indeed need to tie those to VCCIO or GND?