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EBarc1
New Contributor
New ContributorMy 2nd Intel FPGA design
Hello everyone, This is my 2nd usage of an Intel FPGA on a board, and I just want to make sure I'm not making any mistake. On the previous board I used the MAX 10 10M02SC, and now that I need to up...
EBarc1New Contributor
New ContributorHi Chia,
I understand that the 10M02 and 10M04 aren't pin-to-pin compatible. But I'm concerned that maybe the PCB changes needed to migrate to the 10M04 aren't just rerouting the traces & repositioning some components based on the new pin positions of the 10M04. I do believe it's just that. It's just that this is my 2nd design using those FPGAs and I am indeed worried about making a beginner's mistake.
And also, a concern that I have is that the Pin Connection Guidelines for the MAX10 family says that unused CLK and PLL pins should be tied to VCCIO or GND. However, on my previous board, I left them open, and (maybe out of luck) everything worked fine. But do I indeed need to tie those to VCCIO or GND?
