My 1st MAX 10 design

The FPGA clock is at 50MHz, and the fastest signal coming out of the FPGA will be at most 10MHz. Do I need to worry about termination, parallel traces, ground planes (running certain traces adjacent to ground planes for return path impedance matching), or even trace lengths if the longest is ~2cm?

I am keeping clock signals short and as away as possible from other traces, not worrying that much about data signals, and not doing termination at all, with the understanding that 10MHz is nothing to worry that much about.