Honored Contributorquestion: in order to use the quartus ii to do the calculation (multiplication) of floating point, may i know what is the format type used in quartus ii to convert the floating point value to binary? thanks
Honored Contributoryou need create an interface to the megafunction, but the megafunction itself already exists in the altera libraries.
Honored ContributorSorry to ask this, how to create an interface to the megafunction? I never use this function.
for example this is my previous codes: library ieee; use ieee.std_logic_1164.all; library floatfixlib; use floatfixlib.fixed_pkg.all; entity my_mult is port ( clk : in std_logic; a,b : in sfixed(3 downto -4); c : out sfixed(7 downto -8) ); end entity my_mult; architecture rtl of my_mult is begin mult_proc : process(clk) begin if rising_edge(clk) then c <= a * b; end if; end process;Honored Contributoryou are using fixed point, not floating. There is no need to instantiate floating point megafunctions.
But the megawizard creates the files and component declarations you need. You just connect it up with a port map ie.
my_inst : some_entity
port map (
clk => clk,
input1 => signal1,
input2 => signal2
....etc
);
Yes the code above is doing fixed point. i also doing for floating point.
Honored Contributorhow are you doing floating point? the floatfixpkg.float_pkg.all will not produce very good hardware results.
Honored ContributorYeah... i plan to do new program for floating point application. But the problem is i still don't know how to start the programming. i still figure it out. Do you have any sample coding for others application like addition or subtraction? what library to include and the method of writing the code?
Honored ContributorWhat files should added while create a new project wizard?
Honored ContributorYou need to create VHD files from the mega wizard. You should also get a .cmp file, that contains the component declaration. Copy and paste this into your design file, and conecct up the ports something like this:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpadder is
port (
------------------------------------------------------------
--Clock and reset
------------------------------------------------------------
clk : in std_logic;
a,b : in std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
);
end entity;
architecture rtl of fpadder is
component my_fpadder
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
begin
inst1 : my_fpadder
port map (
clock => clk,
dataa => a,
datab => b,
result => c
);
end rtl;
Thanks Tricky. I'll figure it out. Thanks for your help.
