Multiplication on floating point format

You need to create VHD files from the mega wizard. You should also get a .cmp file, that contains the component declaration. Copy and paste this into your design file, and conecct up the ports something like this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fpadder is
  
  port (
    
    ------------------------------------------------------------
    --Clock and reset
    ------------------------------------------------------------
    clk                       : in  std_logic;
    
    a,b                       : in  std_logic_vector(31 downto 0);
    c                         : out std_logic_vector(31 downto 0);
  );
end entity;
  
architecture rtl of fpadder is
  
  component my_fpadder
    PORT
    (
        clock        : IN STD_LOGIC ;
        dataa        : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        datab        : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
        result        : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
    );
end component;
  
begin
  
  inst1 : my_fpadder
  port map (
    clock  => clk,
    dataa  => a,
    datab  => b,
    result => c
  );
  
end rtl;