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VMots
New Contributor
New Contributormultiple timing errors in 10GBASER phy core on clok nets xv_xcvr_10gbaser_nr_inst|ch[*].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|rx_pma.sv_rx_pma_inst|rx_pmas[*].rx_pma.rx_pma_deser|clk90b
Hello! I am developing 10G application on FPGA and I am facing with next problem: I have plenty of timing errors in 10GBASER phy core on clok nets xv_xcvr_10gbaser_nr_inst|ch[*].sv_xcvr_10gbaser_n...
VMotsNew Contributor
New ContributorNevermind, already solve it after write this post.
Problem was in some not working guard variables in sdc files where derive clock was not done, but in timequest was.
Thank you
