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VMots
New Contributor
6 years agomultiple timing errors in 10GBASER phy core on clock nets xv_xcvr_10gbaser_nr_inst|ch[0].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]
multiple timing errors in 10GBASER phy core on clock nets xv_xcvr_10gbaser_nr_inst|ch[0].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst|t...
KhaiChein_Y_Intel
Regular Contributor
6 years agoHi,
You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-timing-analyzer.pdf Chapter 2.4.3 for Overconstrain in Standard edition.
Thanks