multiple timing errors in 10GBASER phy core on clock nets xv_xcvr_10gbaser_nr_inst|ch[0].sv_xcvr_10gbaser_native_inst|native_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]

Thanks for answer, I think overconstraining dramatically increase runtime. I was able to decrease TNS and meet additionally one constraint (from 2 remaining) by simple floorplan with logic lock and design partitioning features, and still going this way.

And if I can ask you - may be you can advise some document which describe methodology of using this features for Quartus Standard 18 or 19?

Thank you again