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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Multiple SERDES in Arria 10

Hello, I am trying to connect 8 4-channel ADC to an Arria 10 FPGA. The ADC (LTC2171-12) has 4 differential LVDS pairs as well as one LVDS pair for the frame clock and one pair for the data clock. ...
Farabi's avatar
Farabi
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,

Yes, you may have issues on resource availability for your implementation.

Referring to below table, IOPLL for your implementation would take bigger size of Arria 10 device.

However, you may take advantage of the transceiver resources to implement LVDS if the IOPLL is not enough.

regards,
Farabi