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Hi htian,
Sorry, I don't understand your two statements:
1) If each bus width is larger than 64, then the 2 controllers on the same side is not much easy. Pin assignment to meet the requirement is the first one to deal with. The IP is not flexbile with 2 ddr controller. You may need to manually add the constraints in the Quartus.
>> What? Do you mean if the total DQ width of your two controllers is greater than the number of available DQ pins?
2) And It looks like the device cannot support 2 controllers use dedicated DQS circuit. So the frequency of ddr2 core cannot higher than 166 M(or 200M?)
>> Again, sorry I don't see your point, I have personally designed StratixII FPGAs with 6 controllers all running at 266MHz, and more recently two controllers at 300MHz on the same side of a single device.
Please clarify your points.
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Hi,
1. no. The bus width of 2 controllers should less than the number of available DQ pins.
First what I said is not to your attached design. We have a design of 2 ddr2 controllers on the same side of EP2S180F1508 (the largest package, I think). Each with 64 bit data bus.
so total is 128 bits. In this case, you cannot directly use the constraints generated by the Megawizard for the 2 ddr2 controllers.
2.
The second one is also based on the design I mentioned above. (I am sorry if I did not make it clear). Quartus cannot let you pass if both controllers (each with 64 bit data bus) use DQS mode. The feedback clock mode will limited the highest frequency of controller.
All the controller I mentioned is based on the version less than 6.1 and not "new" high performance controller.
"more recently two controllers at 300MHz on the same side of a single device."
how wide of the two controllers?
Thanks,
Honored Contributor
