Forum Discussion
Altera_Forum
Honored Contributor
18 years agoHi htian,
Sorry, I don't understand your two statements: 1) If each bus width is larger than 64, then the 2 controllers on the same side is not much easy. Pin assignment to meet the requirement is the first one to deal with. The IP is not flexbile with 2 ddr controller. You may need to manually add the constraints in the Quartus. >> What? Do you mean if the total DQ width of your two controllers is greater than the number of available DQ pins? 2) And It looks like the device cannot support 2 controllers use dedicated DQS circuit. So the frequency of ddr2 core cannot higher than 166 M(or 200M?) >> Again, sorry I don't see your point, I have personally designed StratixII FPGAs with 6 controllers all running at 266MHz, and more recently two controllers at 300MHz on the same side of a single device. Please clarify your points.