Multiple High Speed ADCs via serial LVDS

Hi everybody,

for a new system there is the need to digitize data with 12 Bit/80Msps from up to 20 channels.

To date the idea would be using multiple Quad ADCs with serial LVDS links source synchronous to e.g. a Cyclone V FPGA.

The ADCs could be LT2173-12 (8 data links @ 560 MBit/s each, data frame and clock output available).

All devices are running at the same speed.

I would be very happy to get some insight and comments on the idea, especially the following aspects:

I would use one altlvds_rx instanciation for data reception from each of the ADCs.

Therefore I'd route the data, frame and clock links of each device to a seperate altlvds_rx.

The problem I now see is that when I instanciate one megacore function for each ADC interface, I run out of PLLs (each altlvds_rx consumes 3 generic_pll blocks). Right?

There is the option to share PLLs between multiple receivers. But in this case I think the timing of all devices must be very closely matched as I can not compensate each receiver individually. Am I right?

One solution I was thinking about is driving the input clock to each ADC from a seperate FPGA internal PLL output and use the shared pll approach provided by altpll_rx for data capture.

I could then at least compensate general routing delays between different devices, right?

There may be other solutions by using external PLL devices, perhaps somebody has some good ideas on that.

If I share the plls, are the clock / data outputs on the altpll_rx outputs in sync?

Or do I have to resync them to an additional 80 MHz internal clock?

Is anybody here in this forum who has done such things (maybe with less but also multiple ADC devices :rolleyes:) in the past?

Is the idea completely non sense and simply impossible to get all that data into a single device?

Using multiple single channel ADCs with parallel or DDR interface is no option due to the amount of user IO necessary (there will be other things connected to the FPGA in addition).

Of course I could use several FPGAs but this will blow up board space, power requirements and simply COGS.

Thanks a lot in advance for any comments,

Volker