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The ADC can output the data over 2 lanes, halving the speed requirements to only 480 MBit/s which can be handled, hands down, by a simple deserialiser, using the DCO as the main clock. In a project, a couple of years back now, I deserialised 4 octal ADCs running 50 MHz or 600 MBit/s on an EP2C8F256-C6N. No need for calibration.
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Hi josyb,
Thanks for you informations.
In some 8-channel ADCs, there are two DCO, which means each DCO in charge 4-channel. Same as FCO. So in some cases one fpga maybe want to connect multi-ADC chips, the channels are too much and there are not enough didcated serdes inside FPGA. We need to use DDIO + Shift-Register to receive the ADC data, as attached image shows. It seems we don't need to use the DCO.
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