Multiple High Speed ADCs via serial LVDS

Hi all,

thanks for the big attention :-)

i try to summarize and answer the questions:

@dwh

You're right.

The full bandwidth isn't transmitted from the FPGA.

I can not go into exact details of the project, but the data rate leaving the FPGA is far less then the incoming data rate (averaging of sample trains is performed and a selection / mixture of channels).

In the end 160 MByte/s max. will leave the FPGA which seems to be feasible for current bus technology to handle (e.g. USB 3).

@josyb

thanks for the interesting comments! Bypassing the altlvds_rx function was not an option to me before. Very welcome. This would mean I have my deserializer with the DCO clock which is 560 MHz. Am I right? This looks challenging for a Cyclone on first sight...

@Jerry:

A quad ADCs is used due to system granularity (the system shall be extendable by multiples of four ADC channels. @Jerry Otherwise the Quad LTC one would be have been an option. I do not know the LTM9012 - may be an option, I will check. Thanks for noting!

@FvM

The device transmits 2 Bits in parallel for each channel (two Links in parallel for each channel, "2 lane mode"). Thats why it's feasible on a low cost FPGA from my point of view.

I will go into details regarding the DPA feature.

Thanks again for your very helpfull comments!

I'll be back with new questions if necessary ;-)

Volker