Multiple High Speed ADCs via serial LVDS

Referring to the original post, I don't understand the bitrate calculation. 80 MSPS*12 Bit means 960 Mbit/s, feasible only with Stratix or Arria FPGA families. But these devices could use the SERDES DPA feature and won't need individual PLLs per ADC.

With Cyclone FPGAs, you have preferably a PLL per ADC, clocked by the frame clock output. Using no PLL and both FCO/DCO should work too, but misses an option to fine tune the phase for operation near the FPGA speed limit. Finally, you can generate the receive timing by the PLL driving the ADC, but due to the large propagation delay skew, it won't work a highest speed, as mentioned by josyb.

Or you implement automatic phase calibration (similar to the DPA feature of the hardware LVDS blocks) based on PLL dynamic phase shift and ADC test modes.