multiple driver error during simulation

Ok well trying out some suggestions, I am here with the final code

module test1(si,po,clk,switch,flag);

input si,clk,switch;

output reg [7:0] po;

reg [7:0] c,d;

output reg flag;

reg check;

reg count;

//reg flag;

integer j,i;

initial i=0;

initial flag=0;

initial count=0;

always@(posedge clk)

begin

if(switch==0)

check=1;

if(switch==1 & check==1)

begin

check<=0;

flag<=1;

end

if (flag==1)

begin

c[i]=si;

i=i+1;

///end

if(i==8)

begin

po<=(c[7:4]*10)+c[3:0];

i=0;

flag<=0;

end

end

end

endmodule

Can someone suggest how to optimise this code . I am using a CPLD board which says it requires 94 macrocells for this code but it has got only 64.:)