multiple driver error during simulation

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I am not sure if switch will rise once only or many times.

...etc.

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Yes switch is allowed transitions

"if switch = '1' and switch_d = '0' then" If I am not wrong this is detecting the positive edge

So my count needs to be increased only when there is a positive edge and inputs(serial 8 bits) need to be stored in a reg.

Moreover, me being familiar with Verilog, not VHDL, the syntax

output(count) <= input;

is troubling me