Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start ---
(vhdl clocked process)
--detect edge of switch
switch_d <= switch;
if switch = '1' and switch_d = '0' then
count <= 1;
elsif count < 8 then
count <= count + 1;
end if;
if count < 8 then
output(count) <= input;
end if;
if count = 7 then
valid <= '1';
else
valid <= '0';
end if;
--- Quote End --- As per the specifications the first 8 inputs are to be taken at the positive edge of switch. So why do you set count =1 at +ve edge and increase it by 1 when there's no posedge of switch? 2) if count < 8 then output(count) <= input; end if; what is this used for?