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Altera_Forum's avatar
Altera_Forum
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18 years ago

Multiple Distinct Clocks Error

Hello everyone,

I am trying to write some code to use the debounced keys on the Altera DE2 board. I have spent days on the same error: "Error (10820): Netlist error at lab1.vhd(49): can't infer register for CurAddr[0] because its behavior depends on the edges of multiple distinct clocks" 

process(clock, resetn) 
		variable CurAddr : std_logic_vector(3 downto 0);
		variable CurData : std_logic_vector(7 downto 0);
		variable output : std_logic_vector(6 downto 0);
		begin
		if(clock'EVENT and clock='1') then
			if(key(3)'EVENT and key(3)='0') then 
				if(conv_integer(CurAddr) = 16) then
					CurAddr := "0000";
				end if;
				CurAddr := CurAddr + "0001";
			elsif(key(2)'EVENT and key(2)='0') then
				if(conv_integer(CurAddr) = 0) then
					CurAddr := "1111";
				end if;
				CurAddr := CurAddr - "0001";
			elsif(key(1)'EVENT and key(1)='0') then 
				if(CurData = "11111111") then
					CurData := "00000000";
				end if;
				CurData := CurData + 1;
			elsif(key(0)'EVENT and key(0)='0') then
				if(CurData = "00000000") then
					CurData := "11111111";
				end if;
				CurData := CurData + 1;
			end if;
		end if;
			ram_addr <= CurAddr; --STORE RAM_ADDR
			data_in <= CurData; -- STORE DATA
			hex6 <= led_out1; -- OUTPUT LED CODE
		end process;

I have tried removing the key(#)'EVENT parts. This removes the error but then the Seven Segment Display increments randomly it seems. I am using the 4 keys on the DE2 to control a RAM address and increment or decrement the value in that address. 2 keys to increment/decrement the address and 2 to control the value. I have also tried chaning the variables to signals. This didn't help either. I have also tried changing it to process(key) and removing the 'EVENT part as well as changing key(3)'EVENT to key(3)'last_value='1'. I am having no luck or intelligence. Any suggestions?

Thank you.

V/R,

Alan

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I have the similar error when I try to compile a code to stretch an input pulse for some clock cycles .

    The code compiles and simulates perfectly,except when I add the line "shp_out<=shaped_output"..where I tryto put the signal shaped_output into the port shp_out.

    It gives me an Error (10820):: can't infer register because its behavior depends on the edges of multiple distinct clocks

    entity integrate1 is

    port (

    trig : out std_logic;

    trigger_input,clk_pulse: inout STD_LOGIC

    );

    end integrate1;

    architecture arc of integrate1 is

    signal shaped_output: std_logic:='0';

    signal tmp: std_logic_vector(10 downto 0);

    signal shp_out:std_logic;

    begin

    process (clk_pulse,trigger_input)

    begin

    if (rising_edge(trigger_input)) then

    tmp<="00000000000";

    shaped_output<='1';

    end if;

    if shaped_output='1' then

    if (tmp="00000000100") then

    tmp <= "00000000000";

    shaped_output<='0';

    elsif (clk_pulse'event and clk_pulse='1') then

    tmp <= tmp + 1;

    end if;

    end if;

    end process;

    shp_out<=shaped_output;<<<<<<<<<<----------PROBLEM

    end arc;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Don't use two clocks in the same process. Just read and act on the trigger input inside the "elsif (clk_pulse'event and clk_pulse='1')" part of the process.