Multiple Distinct Clocks Error

I have the similar error when I try to compile a code to stretch an input pulse for some clock cycles .

The code compiles and simulates perfectly,except when I add the line "shp_out<=shaped_output"..where I tryto put the signal shaped_output into the port shp_out.

It gives me an Error (10820):: can't infer register because its behavior depends on the edges of multiple distinct clocks

entity integrate1 is

port (

trig : out std_logic;

trigger_input,clk_pulse: inout STD_LOGIC

);

end integrate1;

architecture arc of integrate1 is

signal shaped_output: std_logic:='0';

signal tmp: std_logic_vector(10 downto 0);

signal shp_out:std_logic;

begin

process (clk_pulse,trigger_input)

begin

if (rising_edge(trigger_input)) then

tmp<="00000000000";

shaped_output<='1';

end if;

if shaped_output='1' then

if (tmp="00000000100") then

tmp <= "00000000000";

shaped_output<='0';

elsif (clk_pulse'event and clk_pulse='1') then

tmp <= tmp + 1;

end if;

end if;

end process;

shp_out<=shaped_output;<<<<<<<<<<----------PROBLEM

end arc;