multiple clock domain instruction

standard is the design name for which ever device you are targeting, and the bdf should be in that directory. did you check:

<Nios II EDS install path>\examples\<verilog or vhdl>\<board

version>\standard

hello

Maybe this thread is useful for you

http://www.alteraforum.com/forum/showthread.php?t=6627&highlight=dabg

Chao

DABG

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standard is the design name for which ever device you are targeting, and the bdf should be in that directory. did you check:

<Nios II EDS install path>\examples\<verilog or vhdl>\<board

version>\standard

--- Quote End ---

thanks for the reply. Exactly, there is such a directory! I thought the bdf file might be there after I generated the updated system using SOPC builder; however, it is not there!! :confused:

where else can i check? thank you

--- Quote Start ---

hello

Maybe this thread is useful for you

http://www.alteraforum.com/forum/showthread.php?t=6627&highlight=dabg

Chao

DABG

--- Quote End ---

Hi, thanks for the link.. sorry that I didn't see the info abt bdf file there. Where could i find it or download it or need to generate or just draw it myself (quite impossible)?

--- Quote Start ---

standard is the design name for which ever device you are targeting, and the bdf should be in that directory. did you check:

<Nios II EDS install path>\examples\<verilog or vhdl>\<board

version>\standard

--- Quote End ---

and there is a bsf file only...

i don't see any bdf files either. the manual must be out dated.

you will have to create the bdf or work with the HDL file instead.

Hello,

I am not sure if I understood your question, but for manage multiple clock domain you can use a double clock fifo.

You can generate this fifo using the MEGAWIZARD PLUG IN MANAGER.

tools>>megawizard plug in manager>>create...>>memory_compiler>>fifo

Good luck.