Multiple ALTGX Channels in Cyclone IV GX

I'm working on a design that uses ALTGX channels to connect several dispersed Cyclone IV GX devices together. I need to have separate receiver/transmitter pairs going to different parts running off separate same-frequency clock sources (give or take crystal oscillator tolerances). We're connecting different pieces of the system using SFP fiber modules, so the ALTGX interface really seems like the way to go.

I've gone through the training presentation and have reviewed the Cyclone IV transceiver chapter but there are some details that are eluding me.

I really don't care about the protocol or latency; perhaps using a standard protocol would be a better way to go. I do need error indication (but not recovery) and it would be helpful to have access to the transceiver toolkit when debugging the system. I need something on the order of 1200-2000 mbps but the specific rate is not important. I'd like to keep everything in VHDL. The link will be managed by a state machine and there won't be a processor available to do any higher level supervision.

If I instantiate two separate ALTGX modules each with one channel, the design doesn't fit, which makes sense because I'm using the 484 pin package which only gives access to one transceiver block.

If I instantiate a two channel ALTGX module with 16-bits datapath, the megawizard block diagram only shows one CDR element and the block has 32-bit width inputs and outputs, which seems to imply that the two channels are operating as a bonded pair rather than as two separate links.

My questions are:

• What is the proper way to instantiate two channels going to two different systems?

• Would it be simpler to use a standard transceiver protocol?

• Has anyone encountered difficulties interfacing SFP modules directly to the ALTGX pins? At a first cut, it looks like all the levels match up fine using AC coupling.

• I'm confused about the documentation block diagrams that show the MPLL adjacent to the transceiver blocks. (a) Are these instantiated as part of the ALTGX or, (b) are you required to instantiate them separately or (c) are these shown to caution users that if you use a PLL to generate the ALTGX base clock you need to use the adjacent MPLLs and their respective clock pins in order to meet the clock jitter specs?

• Are there any other documentation sources that might give a different perspective on using the ALTGX functions, or perhaps provide a checklist? (I took a look through the WIKI and didn't see something that seemed to be relevant)

Thank you in advance for your help!