Multicycle path – enable signal, basic questions

Hello guys,

I have a few basic questions about multicycle paths. I have read many documents (i.e. TimeQuest User Guide) and many threads on this forum which are somehow connected with constraining multicycle paths, but I still have some doubts.

Let’s say I am working with example like this:

process(clk)
begin
if rising_edge(clk) thena_reg   <= a;
b_reg   <= b;
c_reg   <= c;
d_reg   <= d;
e_reg   <= e;
f_reg   <= f;
g_reg   <= g;
h_reg   <= h;
o       <= x1_mul4_x2;
end if;
end process;
a_mul_b    <= a_reg * b_reg;
c_mul_d    <= c_reg * d_reg;
e_mul_f    <= e_reg * f_reg;
g_mul_h    <= g_reg * h_reg;
x1_mul1_x2    <= a_mul_b(2*N-1 downto N) * c_mul_d(2*N-1 downto N);
x3_mul1_x4    <= e_mul_f(2*N-1 downto N) * g_mul_h(2*N-1 downto N);
x1_mul2_x2    <= x1_mul1_x2(2*N-1 downto N) * x3_mul1_x4(2*N-1 downto N); 
x1_mul3_x2    <= x1_mul2_x2(2*N-1 downto N) * x1_mul2_x2(2*N-1 downto N); 
x1_mul4_x2    <= x1_mul3_x2(2*N-1 downto N) * x1_mul3_x2(2*N-1 downto N);

I have clock f = 50 MHz, and after compilation (in Timequest I have constrained only clock), my fmax is ~35 MHz. I do not need to have result on every clock, so to achieve better fmax I can use multicycles.

I have three options and which one is correct in my case?

1. I found somewhere that all I need to do is add multicycle constraints as below, but I read here (http://www.alteraforum.com/forum/showthread.php?t=5576&p=22537#post22537)that multicycles can’t be used in situation where data is changing every clock. And I agree with this. Am I right? Adding only multicycles when all registers are changing every clock is not enough and this is improper use of multicycle constraints (this is not a multicycle)?

However I added constraints, compiled project and got fmax ~ 60 MHz. Is it mistake, because constraints were used wrong?

set_multicycle_path -setup -end -to ~reg0}] 2
set_multicycle_path -hold -end -to ~reg0}] 1

2. Next I decided to add enable signal, but only for destination registers.

enable <= not enable;            
if enable = '1' then
  o  <= x1_mul4_x2;
end if;

Now all source registers are cycled with f = 50 MHz, and destination registers work with f = 25MHz (but clock still is 50 MHz). Can I use here multicycles and will they work properly? I saw a lot of examples where data can be transferred from fast clock domain to slower one. Do I meet this situation here? Can I just add enable signal for destination registers, multicycle constraints and that’s all?

After compilation, I got fmax ~ 60 MHz.

3. I added enable signal to all (source and destination) registers.

enable <= not enable;            
if enable = '1' then
  a_reg    <= a;
  b_reg    <= b;
  c_reg    <= c;
  d_reg    <= d;
  e_reg    <= e;
  f_reg    <= f;
  g_reg    <= g;
  h_reg    <= h;
  o        <= x1_mul4_x2;
end if;

And now I have clear situation. I have multicycle path, where all registers (launch and latch) are clocked with f = 50 Mhz and have enable signal every second cycle.

Can I use multicycles here?

After compilation, I got fmax ~ 60 MHz.

Now to sum up. I described three different cases. When I have data which needs more than one clock cycle to propagate form register to register, the only (best?) solution is to add enable signal to both registers (source and destination) and add multicycle constraints? Third point is the most proper? But what about first two cases? Are they always bad, or they can be also used in some situations? Main question is, source and destination registers should be toggled by enable signal or only destination register has to have enable signal when I want to treat the path as a multicycle?

Regarding point 2. When I transfer data from clk1 to clk2, where source domain is 2x faster (clk1 = 2* clk2), should I add enable signals to registers in clk1 domain? Because I think data should be stable there for two cycles clk1?

Could someone shortly answer to all my question?

Regards,

kolas