Multicycle path – enable signal, basic questions

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Thanks for explanations and ideas,

now I will know what to do with multicycles!

Regards,

kolas

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if your data rate is same as clock rate you should not consider any multicycle at all.

Your problem is that you have two layers of multipliers without registers.Moreover by inferring mults you cannot insert pipeline inside mults.

so having path from input through 2 mults to output is pretty long path. solution insert registers between the two mult stages or even inside mults by instantiating mults with higher latency.