Honored Contributor
Honored ContributorRysc,
I am a little bit confused: --- Quote Start --- If a,b,c,d,etc. have new data every other clock cycle, then Case 3 just ignores every other... --- Quote End --- Shouldn't be there: "every clock cycle"? Because if there were "every clock cycle", everything would be clear for me. I understand that in Case 3, if I have new data on every cycle and enable signal which is high every other cycle, I lose my calculations every other cycle, correct? That is way you wrote --- Quote Start --- ...but wrong for how your design should work --- Quote End --- ? Rest of your post is clear for me. Thanks for sugestions. I never thougth in way that I can add parallel path. Regarding Case 3, to clarify. If I have new data on every clock cycle, I can add enable signal which will generate multicycle paths in the design, but I will loose calculation results every other clock cycle, correct? And last thing. If I have new data on every clock cycle (with no enable signal, so this is Case 1), I can't just add multicycle contraints (because there is no multicycles), I have to redesign the code? Regards, kolas
