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lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
3 years ago

multi-phase clock usage from the same one PLL

I have one question for multi-phase usage of PLL: In the LVDS IP usage, it has soft-cdr mode, and it could process >150Mbps serial siganl without following clock. But for the speed <150Mbps,...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.