Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributormSGDMA stride reads/writes
Has anyone used the Stride feature (available with the extended descriptor)? I using the Qsys PCIe example design on the wiki. When I enable the extended descriptor and stride option, the data tran...
Altera_ForumHonored Contributor
Honored ContributorYES, I DID IT!!
Although I had no clue of verilog and tcl and how to use them in QSYS, I made a conduit from the fifo_usedw wire to the QSYS-System and exported it. Now I can finally see, how many entries in the internal fifo are. Thats nice. With an external Adder-Core I added the Fill-Levels of the original Fifo and the internal fifo of the write-master. Now I have the real amount of stored Data in the FPGA and I can generate DMA-Writes with the exact number of bytes. Thank you
