MSEL clarification for Cyclone III - AS Mode (single device, EPCS) & "sanity check"

Hi all,

Here's a set of "sanity check" questions on a problem we have: We have a custom board using a single Cyc III part, and have been running a version of it with PS mode, and now have updated the board with EPCS and running AS Mode.

Quartus Programmer (v12, also v11) can program the EPCS on our board (it says it's successful). We PoR the board, and it doesn't enter User Mode. We see on logic analyzer the signals nCONFIG and nSTATUS go High, indicating end of Reset phase. But we don't see the nCSO go Low, nor do we see the DCLK or ASDO lines change.

We've checked all the usual suspects (board signal routing, consistency of assignments between Quartus pinout and PCB lines, etc.), and the only thing that gives us pause is the MSEL connections. The signaling we see on the logic analyzer reminds us of PS mode rather than AS mode.

Our Cyc III package doesn't have MSEL[3], and we have MSEL[0] and MSEL[1] driven to GND, for AS mode. The MSEL[2] is connected to VCCINT (1.2v) instead of VCCA (2.5v), which is a problem. We made a quick board change with a resistor so that we could bring VCCINT up to 1.8v, hoping to meet the threshold for this MSEL2.

According to Table 9-7 (Cyclone III Handbk), MSEL bit pattern of 1000 indicates an Active Parallel mode, and 0000 indicates Passive Serial mode; whereas what we want is MSEL = X100 Fast Active Serial Fast mode, assuming the bit-3 is treated as a don't care.

So, the questions are these:

(1) Given that our Cyc III package doesn't support MSEL3, how does the FPGA internal logic treat the don't care status of the MSB of MSEL[3:0]? I can't find any discussion of this anywhere. But the Table 9-7 in Cyc III Handbk is misleading in that it infers one should be able to map all MSEL bits. Does the Cyc III assume MSEL3 is either 0 or 1, or does it treat it a a don't care. Or, does it make a determination as to which mode in indicated with bit-3 based on the listed configuration voltage in Table 9-7, meaning I can change the mode selection based on the voltage level, when I don't have MSEL[3]?

(2) If we're attempting to run the MSEL[2] pin at 1.8v, shouldn't we be able to drive the voltage threshold for the FPGA to interpret that bit to be a logic 1 (thereby indicating that we want AS rather than PS mode)? Note that we're attempting a workaround fix for now, just to get the board to program from EPCS.

(3) Our whole hypothesis as for why the board isn't working is based on the notion that the FPGA is thinking that it should come up in PS mode rather than in AS mode, and that this is why we're not seeing nCSO, DCLK or ASDO signaling from FPGA to EPCS to start configuration phase. Is this a reasonable hypothesis? Anyone have similar experiences?

Lot of stuff here. Thanks for reading and for any cogent thoughts you might have, dear reader.

regds,

jim