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But we don't see the nCSO go Low, nor do we see the DCLK or ASDO lines change
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Given that DCLK does not toggle, it sounds like the (incorrect) MSEL setting is not selecting AS mode.
The Cyclone IV handbook does have comments regarding the missing MSEL MSB on some packages, I didn't look in the Cyclone III handbook to see if that had a similar statement (since you said you'd looked and could not find it).
The handbooks normally state that MSEL high is VCCA, and that the MSEL pins should be tied directly to ground or VCCA. This implies that their thresholds are not normal logic levels, but are pretty close to the stated rails.
I suspect you need to get MSEL[2] tied VCCA before your design will work.
Cheers,
Dave
Honored Contributor
