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Thank you very much folks.
I am still a bit confused about the word glitch. When you read that Mealy machines can cause glitches at the output. Does that imply if the input glitches for whatever reason that glitch will be observed at the output.
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A glitch is temporary unintended change of state in a signal, caused by different delay paths.
Both Moore and Mealy FSMs can produce glitches in their outputs.
In case of Moore FSMs, these come from the skew between FF outputs and also the different delay paths in the output combinational logic.
In the case of a Mealy FSM, in addition to the ones before, the combinational paths from the inputs to the outputs will also produce glitches.
Glitches are common, actually.
One of the advantages of synchronous logic is that, as long as timings are met, glitches will not affect the function of the circuit.
If you can't avoid them, then having your outputs driven directly from registers is a good way to avoid them.
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