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Altera_Forum
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14 years ago

Moore and Mealy

I have been analysing the difference between implementing an identical system using a Moore and a Mealy state machine. The Moore has the advantage of being simpler to implement and more im...
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Altera_Forum
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14 years ago

Read the following document that shows a progression of how to design an interface to a synchronous bus.

Page 31 shows glitches that can be created by using asynchronous state machine outputs.

Note how the FSM designs are a mixture of Mealy and Moore signals, eg., see p35. The Mealy outputs are shown in the ASM charts on transitions, whereas the Moore outputs are within the state boxes. The outputs from either can be registered to ensure they are glitch-free, however, those signals will then be delayed by one clock, so they need to be generated in the ASM chart one clock earlier.

Cheers,

Dave