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Sijith's avatar
Sijith
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Modifying the PCIe DMA transfer example design for Arria 10 device.

Hello, I have a modified version of the PCIe DMA transfer example design (mentioned in the Chapter 7 of attached user manual). As a modification to the example design, I added a custom generated da...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Sijith,


From my understanding, this project has a top level entity as DE5A_NET. Inside the DE5A_NET.v, the ep_g3x8_avmm256 module is included.

That means every change in the ep_g3x8_avmm256.v will reflect in project.

Because the current issue is we want to confirm that the data is written into the memory, I may suggest you to create an EMIF example design and include the rtl code for counter part.

The EMIF example design will include a traffic generator module that will control the Read and Write transaction.


Regards,

Adzim