Modifying the PCIe DMA transfer example design for Arria 10 device.

Hi Sijith,

I have not received the code in the email. Can you send it again in a zip version?

"1) I am curious that since the counter is just streaming data to FIFO (and FIFO does the Avalon MM transfer), do I need to specify any address in my counter code? "

• Maybe not because the counter just providing data. But the module that responsible to perform the write transaction should have it.

"2) If we have a Quartus Project File and associated .qsys file is Opened in the Platform Designer. After adding a new custom IP in the Platform Designer system, Validating system integrity and generating HDL, do we want to do any manual modification in the Verilog code (top-level entity) associated with the Quartus Project? I am aware that generating HDL will create a HDL file in the synthesis directory. Should I use that HDL file as my top level HDL of my Quartus Project?

Is there any reason not to use .qsys file as the top-level entity?"

• You cannot use it directly as top level entity because usually the .qsys file may have some interconnect ports.
• Only the signals that are required for pin connection suppose to be in the top level file.
• If you still encounter the error, please double check the port in top level file and identify for any ports that are not suppose to expose to user logic.

You can refer to Platform Designer User Guide in the link below.

https://www.intel.com/content/www/us/en/docs/programmable/683609/23-1/faq.html

Regards,

Adzim