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Altera_Forum's avatar
Altera_Forum
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14 years ago

ModelSim with VHDL 2008

Peace be upon you;

I am using Quartus II 11.1, ModelSim 10.c (x64), I am used to design my files on Quartus and simulate it on ModelSim using VHDL 2002;

Then I had to move to VHDL 2008 due to some syntax problems, it worked nice with Quartus, but when I try to simulate it on ModelSim, Its compiler can't compile it even if I try to force it to use VHDL 2008, Procedure is as follows:

*Design & Compile on Quartus.

*Run RTL Simulation. --ModelSim is summoned.

*Modelsim's default compilation is VHDL 2002 so it gets errors.

*Adjust ModelSim's compiler options to VHDL 2008.

*Nothing happens.

Thanks in advance.

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The VHDL 2008 support of Modelsim is still pretty limited.

    Check this file for detailed information:

    c:/<modelsim_installation_directory>/docs/technotes/vhdl2008.note
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    10.1 has better support. They have included unconstrained record types (which quartus doesnt support yet)

    What features are you trying to use?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for replying, I've figured out that ModelSim is already compiling with VHDL 2008, but lets consider:

    Type Array_of_STD_LOGIC is Array (Natural Range <>) of STD_LOGIC_VECTOR;

    The previous statement has no problem on Quartus, but with ModelSim -compiling with VHDL 2008- , gives this error:

    Language feature ARRAY ELEMENT SUBTYPE IS UNCONSTRAINED ARRAY is not supported yet.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Well, I moved to the latest versions: Quartus 11.1 SP2 & ModelSim 10.c SP2

    Those are the most latest released, problem still exsisting :(
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Well, I moved to the latest versions: Quartus 11.1 SP2 & ModelSim 10.c SP2

    Those are the most latest released, problem still exsisting :(

    --- Quote End ---

    Don't use that feature then.

    An array of std_logic_vector can be implemented using a bigger std_logic_vector. Use function calls to treat it like an array of arrays.

    Work to the lowest-common-denominator of the tools.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    PE 10.1 is available from the the mentor website (it was released in december - Im using it)

    Is there any reason you are using the 64 bit version? I was told by Mentor that unless you actually need the extra memory, the 32 bit version is better because it runs faster.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    @ dwh@ovro.caltech.edu : Thanks but I really need Array of STD_LOGIC_VECTOR for generic purposes .

    @ Tricky : Thanks, but does the PE version from Mentor website differ from the normal version here at Altera website ?