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nome's avatar
nome
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Modelsim stuck in clock_div loop

Hello I am using Arria FPGA configuration from Max II CPLD with m29ew parallel flash x8 mode I am not using PFL megacore IP. I am using configure fpga by using config_controller.vhd from intel...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,


Let me know if you have any further update or concern?


Thanks,

Best regards,

Sheng