Modelsim stuck in clock_div loop

Hi Nome,

Based on the code provided, I had commented out those two modules config_state_machine and config_control_signal instantiations since not provided.

I noticed you have commented out all the RESET_n port connection and instantiated signal RESET_n to '0' with signal RESET_n : std_logic := '0'; So signal RESET_n will be always '0'. Also, signal MAX_EN is always '0' as well. That's why it will stuck in clock_div loop and keep resetting like below pic.

If instantiated signal RESET_n to '1' with signal RESET_n : std_logic := '1'; It will no more stuck in clock_div loop like below pic.

Thanks,

Best regards,

Sheng

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