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Honored ContributorModelsim: compiling into libraries
Hi all,
I've a few questions regarding Modelsim: 1) libraries contain the VHDL files or the result of the compilation of these files? 2) How can I compile a file in a directory by my choice, different from the work directory? 3) In a testbench, i saw this: library work; use work.lib_one.all; use work.lib_two.all; This means that in work directory there are subdirectories named lib_one, lib_two, and in those subdirectories there were compiled some VHDL files. How can I create subdirectories of WORK and compile there VHDL files? Thanks a lot for your answers.12 Replies
Altera_Forumyou're right,
i've compiled another file with the same name 'log_package.vhd', but different code is there a way to compile all files in a folder in just one command? thank you very much Tricky- Altera_Forum
All compiles fine for me.
are you sure you've compiled log_package.vhd? - Altera_Forum
thank u very much
- Altera_Forum
can you zip up all the source and post here?
- Altera_Forum
i've compiled it, and other files, using the command u told me earlier:
vcom C:/utils_package.vhd vcom c:/log_package.vhd vcom C:/bus_control_package.vhd vcom C:/clock_sim_package.vhd ... and in the top: library work;use work.log_package.all;
use work.clock_sim_package.all;
use work.reset_sim_package.all;
use work.utils_package.all;--
use work.serial_io_mux_package.all;
use work.serial_io_demux_package.all;
- Altera_Forum
have you included the log_package?
library wherever_log_package_is_lib; use wherever_log_package_is_lib.log_package.all; - Altera_Forum
Very good...that was the problem...sorry, i'm a newer in VHDL and Modelsim :)
but now I've got another problem...the last one: In one package, i've declared: package log_package is procedure log_write(level_i : in integer; from_i : in string; str_i : in string);procedure log_write(level_i : in integer; from_i : in string; bus_command_i : in t_bus_command);
procedure log_write(level_i : in integer; from_i : in string; bus_result_i : in t_bus_result); end log_package; ... so three procedures with the same name, but different input parameters; in my top I've written: entity top is ... end; architecture arch_top of top is ...<signals>... begin ... myprocess : process procedure writetestresult(test_name_i : in string; result_i : in boolean) is
begin
if result_i then
log_write(log_level_essential,instance_name,"passed " & test_name_i);
else
log_write(log_level_essential,instance_name,"failed " & test_name_i);
end if;
end procedure writetestresult; begin ... end process myprocess; end arch_top; Modelsim get me an error: ** Error: (vcom-1136) Unknown identifier "log_write". Where am I going wrong?
- Altera_Forum
have you created a lib_one library? have you done this in your top.vhd file?
library lib_one; use lib_one.CLOCK_SIM_PACKAGE.all; - Altera_Forum
Thank you very much.
Now I've another problem: I've compiled a library into a folder with this command: vcom -reportprogress 300 -work lib_one c:/component.vhd Component.vhd contains this component: package clock_sim_package iscomponent clock_sim
generic
(
constant freq : integer:=10000000;
constant duty : integer:=50
);
port
(
enable : in std_logic;
output : out std_logic
);
end component;
end clock_sim_package; library ieee;
use ieee.std_logic_1164.all; entity clock_sim is
generic
(
constant freq : integer:=10000000;
constant duty : integer:=50
);
port
(
enable : in std_logic;
output : out std_logic
);
end clock_sim; architecture clock_sim_arch of clock_sim is
begin
mainprocess : process
constant rduty : real:=real(duty)/100.0;
constant tclkh : time:=1 sec*((1.0/real(freq))*rduty);
constant tclkl : time:=1 sec*((1.0/real(freq))*(1.0-rduty));
begin
if enable='1' then
output<='1';
wait for tclkh;
output<='0';
wait for tclkl;
else
wait until enable='1';
end if;
end process mainprocess;
end clock_sim_arch; Into the top I instanciate the component (under architecture..begin): the_clock : clock_sim
generic map
(
duty=>50,
freq=>clock_freq
)
port map
(
enable=>'1',
output=>clk
); but when I try to compile the top, this is the answer: ** Error: Identifier "clock_sim" does not identify a component declaration. What am I doing wrong?
- Altera_Forum
lib_one is not a library, it is a package in the library "work".
all you have to do is run: vcom lib_one.vhd (or wherever the file lib_one.vhd is) and it will compile it into the work library.
