Modelsim: compiling into libraries

Thank you very much.

Now I've another problem:

I've compiled a library into a folder with this command:

vcom -reportprogress 300 -work lib_one c:/component.vhd

Component.vhd contains this component:

package clock_sim_package is

component clock_sim

generic

(

constant freq : integer:=10000000;

constant duty : integer:=50

);

port

(

enable : in std_logic;

output : out std_logic

);

end component;

end clock_sim_package;

library ieee;

use ieee.std_logic_1164.all;

entity clock_sim is

generic

(

constant freq : integer:=10000000;

constant duty : integer:=50

);

port

(

enable : in std_logic;

output : out std_logic

);

end clock_sim;

architecture clock_sim_arch of clock_sim is

begin

mainprocess : process

constant rduty : real:=real(duty)/100.0;

constant tclkh : time:=1 sec*((1.0/real(freq))*rduty);

constant tclkl : time:=1 sec*((1.0/real(freq))*(1.0-rduty));

begin

if enable='1' then

output<='1';

wait for tclkh;

output<='0';

wait for tclkl;

else

wait until enable='1';

end if;

end process mainprocess;

end clock_sim_arch;

Into the top I instanciate the component (under architecture..begin):

the_clock : clock_sim

generic map

(

duty=>50,

freq=>clock_freq

)

port map

(

enable=>'1',

output=>clk

);

but when I try to compile the top, this is the answer:

** Error: Identifier "clock_sim" does not identify a component declaration.

What am I doing wrong?