Honored Contributor
Honored ContributorA table (memory) with the delays is a good way to handle it, if you want to have it in hardware.
Actually, thinking back, I think I've never implemented a exponential distribution in Verilog. So far, my test benches involving exponential distributions were VHDL; there's native support through the ieee.math_real package. A bit of googling led me to conclude that even SystemVerilog still lacks a functions for real math and you need to use DPI or PLI. That said, another approach I take to pseudo-random data generation for testbenches is to do write a small program (in C++ or whatever you feel confontable with) to generate test data into files and then have my Verilog/VHDL test bench read those files.
