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Altera_Forum
Honored Contributor
Honored ContributorMixing VHDL and Verilog
I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins. I have a VHDL file that instantiates this Verilog top module to get acc...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The board is the Cyclone V GX Starter Kit. --- Quote End --- This Terasic board: http://www.altera.com/products/devkits/altera/kit-terasic-cyclone-v-gx-starter.html This looks similar to their DE-series of boards. Terasic usually have a golden-top reference design. I usually synthesize that, export the design as Tcl, and then write scripts like that for the BeMicro-CV design I linked to above. I then go through the schematic and check the pin assignments and add any missing pin constraints. You should be able to duplicate something similar for your own use. Cheers, Dave
