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Altera_Forum's avatar
Altera_Forum
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11 years ago

Mixing VHDL and Verilog

I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins. I have a VHDL file that instantiates this Verilog top module to get acc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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If the signal names are identical, then yes, it would work fine, however, its a bit redundant right?

I also code in VHDL. My personal philosophy with reference designs (Altera and Terasic) is that they are a starting-point. I take their golden-top reference design, synthesize that project (which does not always succeed), and then export all the project constraints. I take the pin assignments for the board and move that to a separate script (constraints.tcl), and then create a top-level 'basic' design, and use that as a template for all other designs.

Take a look at the bemicro_cv_examples.zip file in this thread:

http://www.alteraforum.com/forum/showthread.php?t=43992

What I'd recommend you do, is create a top-level pin constraints script based on the Terasic reference documentation, and your own VHDL top-level design, and they you no longer need to use any of the Terasic resources.

If this sounds too complicated, point me to the Terasic board you have, and I'll give you more detailed instructions.

Cheers,

Dave

PS. If the file is not too big, you can zip it (or Quartus archive it) and send it to me, and I'll see if I can see what is wrong. My forum name is my email address.

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Thanks. I try your suggestion.

The board is the Cyclone V GX Starter Kit.