Missing virtual jtag documentation

Is it just me or does anybody else think that this is a serious oversight from Altera. Why they don't just they let you see the actual JTAG pins is beyond me??

At this stage I am thinking that maybe it is worth replacing the SOPC JTAG UART with the Avalon BFM for simulation purposes.

However this would mean that the actual design post place and route would not have the ability to have back annotated SDF timing simulations applied to it.

For a worst case timing/temperature/etc I have always been told that this is a necessary part of sign-off.

Ideally, I am after a solution for this which talks with the ACTUAL design so that you can then run both RTL and back annotated timing simulations in Modelsim.

Does anybody have any further ideas??

How do other people do this? or Is it just NOT possible with a NIOSII design??

Its a bit bad if this is the case in my eyes...