Missing virtual jtag documentation

Are you trying to simulate the VJI because it has bugs, or just replicate what you're doing via VJI to get the system to work(i.e. read and write some registers)? Since VJI ends up having you create the final layer of logic i.e. your instruction and data chains within the fabric, why not just have those be your interface for your commands, i.e. during simulation have those registers just appear(and don't include the actual VJI guts in your RTL sim). My guess is that will run much faster than taking hundreds of clock cycles to serially load in a single command.

A problem with having an RTL model for VJI is that it would be a model up to the JTAG ports on the FPGA. There is a large gap between the Tcl commands you type in the console and how those get translated to TDI ticks. Whatever was done would be slow and would certainly not be cycle accurate with how your computer software operates. I think just removing the VJI directly would be the best bet.