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Altera_Forum
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15 years ago

minimum time for IO pin to damage

hello all, there is a question about the minimum time for an IO pin of the FPGA like the cyclone EP1C6Q240.. I want to know the min. time for the pin to damage when it is exposed to a vo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

You have to judge the risk of ESD damage with your design. Second protection level would involve e.g. ESD diode, series resistor, second diode respectively clamp circuit.