Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

minimum time for IO pin to damage

hello all, there is a question about the minimum time for an IO pin of the FPGA like the cyclone EP1C6Q240.. I want to know the min. time for the pin to damage when it is exposed to a vo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The datasheet doesn't say anything about what happens if you go outside the -0.5 to 4.1V range so I don't think you can have any guarantee when you exceed them. It could be a good idea to use clamping diodes instead of a zener or surge protection diode.

When I have enough space on the board I prefer to put a buffer between the FPGA and any signal that can be exposed to ESD. Buffers are inexpensive and tolerate more on their pins.