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Honored Contributor
Honored ContributorMinimum pulse width error
Hi, I am geting a minimum pulse width error when I am trying to send a clock signal throw my fpga. verilog code: module top ( input CLK_125, output TX_CLK ); alw...
Altera_ForumHonored Contributor
Honored ContributorMinimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell’s internal operations to complete. i.e. to get a stable output you need to ensure that the clock signal at the clock pin of the flop is at least of a certain ‘minimum’ width.
You get this error from TimeQuest due to the fact that the required time (13ns)is greater than the actual time(8ns). You need to constrain the clock pins with the minimum pulse width constraint. For the clock signal to be passed successfully, the Actual time should be greater than the required time so that you meet the minimum pulse width requirements. set_min_pulse_width -high 4.0 [all_clocks] set_min_pulse_width -low 4.0 [all_clocks]
