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Altera_Forum's avatar
Altera_Forum
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8 years ago

Minimum pulse width error

Hi, I am geting a minimum pulse width error when I am trying to send a clock signal throw my fpga. verilog code: module top ( input CLK_125, output TX_CLK ); alw...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Increase the drive strength on TX_CLK to maximum.

Cheers,

Alex

--- Quote End ---

Changed current strenght from "2mA(default)" to "Maximum Current". It did not change anything.

But, thanks for the answer