Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi,
We are still investigating the issue. We found out that by touching pins D0 or D1 of the EPCQ32A device with an oscilloscope probe during the configuration phase, the FPGA immediately loads the configuration data and configuration is successful. This suggests that we are facing a signal integrity issue. Warm boards (and devices) work better than cold ones. Adding 10pF 0603 capacitors between each Dx signal and GND on the EPCQ32A pins seems to mitigate our issue (on most boards the FPGA loads the configuration data at the first attempt). However, we are yet to find a solution that works on any board and at any temperature (say -10 to 40°C). We do not have series resistors on D0-D3, nCS and DCLK between the EPCQ32A and the 5CEBA2F17C7N FPGA. We have a 6-layer board, ground plane with no interruptions. Track lengths (between flash and FPGA) are as follows: pin sig mm 1 nCS 17.9 2 D1 18.6 3 D2 22.9 4 GND 5 D0 14.3 6 CLK 15.4 7 D3 11.7 8 3V3 2 vias per signal. track widths: 8mil VCC (flash and FPGA I/O banks): 3V3 Please note that an EPCQ32 flash works while an EPCQ32A flash fails to configure the FPGA (on the very same board). Maybe the EPCQ32 has more relaxed rise/fall times than the EPCQ32A (the datasheets do not provide any data about the device's rise/fall times) Configuration clock frequency: does not have any impact. A view of the PCB is attached (D0-D4, nCS and DCLK are highlighted). Red: top Blue: bottom Brown: intermediate signal plane In our view, the tracks are relatively short and we would not have expected signal integrity issues, although this seems to be the case. Are there any guidelines for the PCB layout of the EPCQ-A memory signals? Do the EPCQ-A need a by-pass capacitor? We put a 100nF, 0603 between VCC and the ground plane, with very short tracks. Is 100nF enough? The EPCQ-A datasheet does not mention it, nor it provides PCB layout guidelines. Are series resistors recommended? Any advice? Thanks, Best regards, Matteo