Forum Discussion
Altera_Forum
Honored Contributor
7 years agoHi Carlhermann,
correct, we only have the JTAG interface on the board. The AS interface is between the FPGA and the EPCQ32A: there are no connectors or other devices connected to the AS interface, besides the EPCQ32A and the Cyclone V. We captured the signals nCS, DCLK, DATA0 and DATA1 at board power up. The FPGA sends the following Operation codes to the EPCQ32A memory: - 05h, read status. Reply: zero - 9Fh, read device identification: reply 16h, which is correct (EPCQ32 and EPCQ32A have the same ID according to their datasheets) - 0Bh, fast read (from address zero): the memory replies with some data - EBh, extended quad input fast read: the memory replies with some data, but then after approximately 220 bytes the FPGA raises nCS and the operation is aborted. (with the EPCQ32, this last operation lasts until all configuration data is transferred from the memory to the FPGA) The last operation code is executed at the clock frequency set in Device Configuration in Quartus, whereas the previous operation codes are executed at 12.5 MHz (nominal). We already raised a "MySupport" issue for our original problem (i.e. the FPGA cannot load the configuration data from the EPCQ32A). We are currently awaiting a reply. Thanks, Regards.